信號(hào)完整性設(shè)計(jì)工程師
面議
大連
5年以上
碩士
大連
5年以上
碩士
- 全勤獎(jiǎng)
- 節(jié)日福利
- 不加班
- 周末雙休
- 五險(xiǎn)一金
最近更新
2640人關(guān)注
職位描述
該職位還未進(jìn)行加V認(rèn)證，請(qǐng)仔細(xì)了解后再進(jìn)行投遞！
職位描述：
1. high speed channel design, characterization, optimization, and correlation
2. parallel buses, ddr3/4 etc., timing and signal quality design and analysis
3. pdn dc drop and ac design and analysis, including decoupling capacitors selection and placement, also power plane optimization1. 1. master degree or above. 5+ years of experience in signal integrity design and verification, including 2+ years in system level
2. deep knowledge on transmission line theory, electromagnetic field theory and time & frequency domain analysis.
3. experiences with high speed digital board design.
4. experiences with major si/pi tools: cadence allegro, hyperlynx, sisoft, sigrity, ads, hfss, cst etc..
5. lab measurement experience with oscilloscopes, spectrum analyzers and vnas.
1. high speed channel design, characterization, optimization, and correlation
2. parallel buses, ddr3/4 etc., timing and signal quality design and analysis
3. pdn dc drop and ac design and analysis, including decoupling capacitors selection and placement, also power plane optimization1. 1. master degree or above. 5+ years of experience in signal integrity design and verification, including 2+ years in system level
2. deep knowledge on transmission line theory, electromagnetic field theory and time & frequency domain analysis.
3. experiences with high speed digital board design.
4. experiences with major si/pi tools: cadence allegro, hyperlynx, sisoft, sigrity, ads, hfss, cst etc..
5. lab measurement experience with oscilloscopes, spectrum analyzers and vnas.
注：聯(lián)系我時(shí)，請(qǐng)說是在四川人才網(wǎng)上看到的。
工作地點(diǎn)
地址：大連甘井子區(qū)北京-朝陽區(qū)
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詳細(xì)位置，可以參考上方地址信息
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職位發(fā)布者
HR
大連檸檬信息技術(shù)有限公司
-
計(jì)算機(jī)軟件
-
21-50人
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公司性質(zhì)未知
-
數(shù)碼廣場(chǎng)軟件園8號(hào)樓
